
then presented to the first-stage quantizers and isolate
the pipelines from the fast-changing inputs. Analog
inputs, IN_P to IN_N, are driven differentially. For differ-
ential inputs, balance the input impedance of IN_P and
IN_N for optimum performance.
Reference Configurations (REFIO,
REFADJ, REFP, and REFN)
The MAX1434 provides an internal 1.24V bandgap ref-
erence or can be driven with an external reference volt-
age. The full-scale analog differential input range is
±FSR. FSR (full-scale range) is given by the following
equation:
where VREFIO is the voltage at REFIO, generated inter-
nally or externally. For a VREFIO = 1.24V, the full-scale
input range is ±700mV (1.4VP-P).
Internal Reference Mode
Connect REFADJ to GND to use the internal bandgap
reference directly. The internal bandgap reference gen-
erates VREFIO to be 1.24V with a 120ppm/°C tempera-
ture coefficient in internal reference mode. Connect an
external
≥ 0.1F bypass capacitor from REFIO to GND
for stability. REFIO sources up to 200A and sinks up
to 200A for external circuits, and REFIO has a
75mV/mA load regulation. REFIO has > 1M
to GND
when the MAX1434 is in power-down mode. The inter-
nal reference circuit requires 100ms (CREFP to GND =
CREFN to GND = 1F) to power up and settle when
power is applied to the MAX1434 or when PD transi-
tions from high to low.
To compensate for gain errors or to decrease or
increase the ADC’s FSR, add an external resistor
between REFADJ and GND or REFADJ and REFIO.
This adjusts the internal reference value of the
MAX1434 by up to ±5% of its nominal value. See the
Full-Scale Range Adjustments Using the Internal
Reference section.
FSR
V
REFIO
=
×
(.
)
.
0 700
124
MAX1434
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________________________
13
MAX1434
IN_P
IN_N
OTA
AVDD
GND
C2a
S4b
S4c
S1
C2b
S4a
C1a
S2a
S5a
S3a
S3b
S5b
C1b
S2b
INTERNAL
BIAS*
OUT
INTERNALLY
GENERATED
COMMON-MODE
LEVEL*
SWITCHES SHOWN IN TRACK MODE
INTERNALLY
GENERATED
COMMON-MODE
LEVEL*
INTERNAL
COMMON-MODE
BIAS*
INTERNAL
COMMON-MODE
BIAS*
*NOT EXTERNALLY ACCESSIBLE
INTERNAL
BIAS*
OUT
Figure 1. Internal Input Circuit